Adaptive algorithm and tool flow for accelerating SystemC on many-core architectures

We present a highly parallel SystemC RTL simulator with full delta cycle accuracy.Asynchronous and decentralized synchronization concept for many-core architectures.An automated tool-flow combines model analysis and parallel SystemC simulation.The analysis tool enables adaption of the synchronization system to the model.We achieved a speedup of 29.3 using 47 cores instead of a single processor. Within this article an adaptive approach for parallel simulation of SystemC RTL models on future many-core architectures like the Single-chip Cloud Computer (SCC) from Intel is presented. It is based on a configurable parallel SystemC kernel that preserves the partial order defined by the SystemC delta cycles while avoiding global synchronization as far as possible. The underlying algorithm relies on a classification of existing communication relations between parallel processes. The type and topology of communication relations determines the type and number of causality conditions that need to be fulfilled during runtime. The parallel kernel is complemented by an automated tool flow that allows detecting relevant model-specific properties, performing a fine-grained model partitioning, classifying communication relations and configuring the kernel. Experiments by means of a MPSoC model show that pure local synchronization can provide significant performance gains compared to global synchronization. Furthermore, the combination of local synchronization with fine-grained partitioning provides additional degrees of freedom for optimization.