Whitespace-Aware TSV Arrangement in 3-D Clock Tree Synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1842-1853, 2015.

Cited by: 4|Bibtex|Views27|Links
EI WOS
Keywords:
Through-silicon viasClocksCouplingsMergingTopologyMore(2+)
Weibo:
The algorithm consists of three stages: sink pre-clustering, TWA-3D-method of means and medians topology generation, and deferred-merge embedding merging segment reconstruction

Abstract:

Through-silicon-via (TSV) could provide vertical connections among different dies in 3-D integrated circuits (3-D ICs), but the significant silicon area occupied by TSVs may bring great challenge to designers in 3-D clock tree synthesis (CTS), because only a few whitespace blocks can be used for clock TSV insertion after floorplan and pla...More

Code:

Data:

0
Introduction
  • As CMOS process technology continuously scaling down, through-silicon-via (TSV) based three-dimensional integrated circuits (3D ICs) have drawn much more attention recently.
  • TSVs are usually placed in the whitespace among macro blocks or cells, a bad arrangement of TSVs may incur longer wirelength since the available TSV might be far away from its connected cells.
  • Intellectual Property (IP) and Standard cell based design has been extensively used to reduce design cost, but after floorplan and placement, only few whitespace blocks are reserved for clock TSVs [3].
Highlights
  • As CMOS process technology continuously scaling down, through-silicon-via (TSV) based three-dimensional integrated circuits (3D ICs) have drawn much more attention recently
  • In the TWA-3D-method of means and medians (MMM) clock tree topology generation stage, we extend the 3D-MMM method by judging whether the current x/y-cut between multiple dies is appropriate, considering whitespace to ensure that each sink set contains whitespace
  • Different from the existing 3D design, which focused on slew-aware buffer insertion during the bottom-up embedding procedure of deferred-merge embedding (DME) [5, 11, 12], our slew-aware buffering is performed after clock routing for the following reasons: 1) it is easy to achieve with an O(n) time complexity; 2) the buffer delay may change under different supply voltage, so exact zero skew numerical buffer solution during bottom-up embedding procedure of DME under one supply voltage may change under another
  • The algorithm consists of three stages: sink pre-clustering, TWA-3D-MMM topology generation, and DME merging segment reconstruction
  • We propose a whitespace-aware 3D clock tree synthesis (CTS) flow
  • Experiment results show that our method is more practical and efficient, compared to the traditional 3D-MMM based one with TSV moving adjustment
Results
  • After exhaustively sweeping the TSV bound from 1 to 50 the authors observe that in Fig. 9, as the TSV bound increase little by little, the 3D-MMM-DBM solutions suffer from severe power and skew problems, while the method shows consistent good results
  • This is not difficult to imagine because a larger TSV bound means more TSV moving adjustment, which may worsen clock latency unbalance.
  • The authors will consider more cases such like multiple dies, uneven sink distribution, and explore the dependency of the whitespace and #TSV with the power reduction in the future work
Conclusion
  • The authors formulate the whitespace-aware TSV arrangement problem in 3D CTS and propose a practical and efficient algorithm to deal with it.
  • The algorithm consists of three stages: sink pre-clustering, TWA-3D-MMM topology generation, and DME merging segment reconstruction.
  • The authors propose a whitespace-aware 3D CTS flow.
  • Experiment results show that the method is more practical and efficient, compared to the traditional 3D-MMM based one with TSV moving adjustment
Summary
  • Introduction:

    As CMOS process technology continuously scaling down, through-silicon-via (TSV) based three-dimensional integrated circuits (3D ICs) have drawn much more attention recently.
  • TSVs are usually placed in the whitespace among macro blocks or cells, a bad arrangement of TSVs may incur longer wirelength since the available TSV might be far away from its connected cells.
  • Intellectual Property (IP) and Standard cell based design has been extensively used to reduce design cost, but after floorplan and placement, only few whitespace blocks are reserved for clock TSVs [3].
  • Results:

    After exhaustively sweeping the TSV bound from 1 to 50 the authors observe that in Fig. 9, as the TSV bound increase little by little, the 3D-MMM-DBM solutions suffer from severe power and skew problems, while the method shows consistent good results
  • This is not difficult to imagine because a larger TSV bound means more TSV moving adjustment, which may worsen clock latency unbalance.
  • The authors will consider more cases such like multiple dies, uneven sink distribution, and explore the dependency of the whitespace and #TSV with the power reduction in the future work
  • Conclusion:

    The authors formulate the whitespace-aware TSV arrangement problem in 3D CTS and propose a practical and efficient algorithm to deal with it.
  • The algorithm consists of three stages: sink pre-clustering, TWA-3D-MMM topology generation, and DME merging segment reconstruction.
  • The authors propose a whitespace-aware 3D CTS flow.
  • Experiment results show that the method is more practical and efficient, compared to the traditional 3D-MMM based one with TSV moving adjustment
Tables
  • Table1: IMPACT OF DIFFERENT WHITESPACE AREA ON #TSV, SKEW, POWER AND SLEW BETWEEN 3D-MMM-DBM METHOD AND OUR PROPOSED METHOD (TSV BOUND IS SET TO BE 20, #BLOCK AND #TSV MEANS THE NUMBER OF WHITESPACE BLOCKS AND TSVS, VIO MEANS SLEW VIOLATION)
  • Table2: IMPACT OF DIFFERENT TSV BOUND ON DIFFERENT BENCHMARKS BETWEEN 3D-MMM-DBM AND OUR METHOD
Download tables as Excel
Funding
  • This work was supported by National Science and Technology Major Project (2010ZX01030-001-001-04, 2011ZX01035-001-001-002), National Natural Science Foundation of China (No 61261160501, 61028006, 61076035), and Tsinghua University Initiative Scientific Research Program
Reference
  • Y. Xie, G. Loh, B. Black, and K. Bernstein, “Design space exploration for 3d architectures,” ACM Journal on Emerging Technologies in Computing Systems, vol. 2, no. 2, pp. 65–103, April 2006.
    Google ScholarLocate open access versionFindings
  • M. Pathak, Y.J. Lee, T. Moon, and S.K. Lim, “Throuth-Silicon-Via management during 3D physical design: when to add and how many?”, in ICCAD, November 2010, pp. 387-394.
    Google ScholarFindings
  • M.K. Hsu, Y.W. Chang, and V. Balabanov, “TSV-aware analytical placement for 3D IC design”, in DAC, June 2011, pp. 664-669.
    Google ScholarFindings
  • J. Minz, X. Zhao, and S. K. Lim, “Buffered clock tree synthesis for 3D ICs under thermal variations”, in ASPDAC, March 2008, pp. 504-509.
    Google ScholarLocate open access versionFindings
  • X. Zhao, J. Minz, and S.K. Lim, “Low-power and reliable clock network design for Through-Silicon Via (TSV) based 3D ICs”, IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 1, no. 2, pp. 247-259, February 2011.
    Google ScholarLocate open access versionFindings
  • T.Y. Kim and T. Kim, “Clock tree embedding for 3D ICs,” in ASPDAC, January 2010, pp.486-491.
    Google ScholarFindings
  • X. Zhao and S.K. Lim, “Through-Silicon-Via-induced obstacle-aware clock tree synthesis for 3D ICs”, in ASPDAC, Feb. 2012, pp. 347-352.
    Google ScholarFindings
  • M.C. Tsai, T.H. Wang, and T.T. Huang, “Through-Silicon Via planning in 3-D floorplanning”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 8, pp. 1448-1457, August 2011.
    Google ScholarLocate open access versionFindings
  • M.A.B. Jackson, A. Srinivasan, and E.S. Kuh, “Clock routing for highperformance ICs”, in DAC, June 1990, pp. 573-579.
    Google ScholarFindings
  • T.H. Chao, Y.C. Hsu, J.M. Ho, and A.B. Kahng, “Zero skew clock routing with minimum wirelength”, IEEE Transactions on Circuits and Systems II, vol. 39, no.11, pp. 799-814, November 1992.
    Google ScholarLocate open access versionFindings
  • X. Zhao, D.L. Lewis, H.H.S. Lee, and S.K. Lim, “Low-power clock tree design for pre-bond testing of 3-D stacked ICs”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 5, pp. 732-745.
    Google ScholarLocate open access versionFindings
  • F.W. Chen, and T.T. Hwang, “Clock tree synthesis with methodology of re-use in 3D IC”, in DAC, June 2012, pp. 1094-1099.
    Google ScholarFindings
  • ISPD 2009 Clock Network Synthesis Contest benchmark. http://ispd.cc/contests/09/ispd09cts.html
    Findings
  • Predictive Technology Model. http://ptm.asu.edu/
    Findings
  • NGSPICE http://ngspice.sourceforge.net/
    Findings
Your rating :
0

 

Tags
Comments