Hybrid LUT/Multiplexer FPGA Logic Architectures.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems(2016)

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摘要
Hybrid configurable logic block architectures for field-programmable gate arrays that contain a mixture of lookup tables and hardened multiplexers are evaluated toward the goal of higher logic density and area reduction. Multiple hybrid configurable logic block architectures, both nonfracturable and fracturable with varying MUX:LUT logic element ratios are evaluated across two benchmark suites (VT...
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关键词
Table lookup,Field programmable gate arrays,Delays,Routing,Transistors,Logic gates
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