An Amplifier-Free Pipeline-SAR ADC Architecture With Enhanced Speed and Energy Efficiency.
IEEE Transactions on Circuits and Systems II: Express Briefs(2016)
摘要
A new pipeline-successive approximation register (SAR) analog-to-digital converter (ADC) structure without residue amplifier and timing-interleaving is presented in this brief. Two redistribution digital-to-analog converters (DACs) and comparators are adopted in two stages, with DAC1 for most significant bit (MSB) comparisons and DAC2 for least significant bit (LSB) comparisons. The previous sampl...
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关键词
Switches,Calibration,Capacitance,Capacitors,Power demand,Timing
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