Comparator Power Minimization Analysis for SAR ADC Using Multiple Comparators

Comparator power consumption is a major bottleneck to the power efficiency of a high resolution successive approximation register (SAR) analog-to-digital converter (ADC) used in low-power applications. This paper analyzes theoretically the optimal comparators that need to be used to achieve a desired overall performance at minimum power levels. A simple and accurate mathematical model of the SAR A...