Tutorial: Post-Silicon Validation And Diagnosis

2016 29TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2016 15TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID)(2016)

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摘要
With increase in design complexity, aggressive scaling and decrease in time to market have resulted in escalation of functional and manufacturing errors in the design. Post-silicon validation and diagnosis deal with functional and manufacturing faults respectively in the manufactured chip. The major difference between dealing with these two types of faults is the way they are tested. Since functional errors are replicated, testing only one chip out of a die is sufficient. On the other hand, in case of manufacturing errors, all the chips have to be individually tested as manufacturing errors vary from one chip to another. A vast majority of the functional faults are captured during the pre-silicon phase. However, it is extremely expensive to find and fix these small percentages of remaining faults. Studies indicate that post-silicon validation consumes about 50% of a SoCs overall design cost at 65nm technology, and the cost increases with reduction in size; thus, projecting it as one of the most important phases of the design cycle. Fault diagnosis also plays a major role in fast yield ramp up. Information provided by the diagnosis process is used to guide the physical failure analysis (PFA) tools. With the increasing complexity in logic design, physical inspection in today's multi-layer deep sub-micron devices has become exceedingly expensive and time-consuming. Therefore, improving the efficiency and accuracy of fault diagnosis is necessary for the yield ramping-up.This tutorial focuses on recent research works and state of the art industry practices in the fields of post-silicon validation and diagnosis. The post-silicon validation part focuses on signal selection, trace debug, trace compression, test generation; while the diagnosis deals with both logic and chain diagnosis. It also focuses on diagnosis techniques with test-response compressors, which is widely used in recent industrial design. The tutorial presenters (received PhD degree in recent times (2-3 years) and since been working on the similar domains in the state of the art industrial solutions) will be able to provide unique perspectives on both academic research and industrial practices. The selection of topics covers a broad spectrum and will be of interest to a wide audience including design, validation, and, test engineers as well as young researchers.
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