ESD design automation & methodology to prevent CDM failures in 130 & 90 nm ASIC design systems
Journal of Electrostatics, pp. 112-127, 2006.
Design automation tools for ESD are described that ensure robust protection at both the cell and chip level in a high-volume, highly automated ASIC design system. The Charged Device Model (CDM) failure modes discovered in the 130nm technology are described, and the design automation tools that were implemented to prevent these failures ar...More
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