Design And Implementation Of A High Sensitivity Fully Integrated Passive Uhf Rfid Tag

A fully integrated passive UHF RFID tag complying with the ISO18000-6B protocol is presented, which includes an analog front-end, a baseband processor, and an EEPROM memory. To extend the communication range, a high efficiency differential-drive CMOS rectifier is adopted. A novel high performance voltage limiter is used to provide a stable limiting voltage, with a 172 mV voltage variation against temperature variation and process dispersion. The dynamic band-enhancement technique is used in the regulator circuit to improve the regulating capacity. A rail-to-rail hysteresis comparator is adopted to demodulate the signal correctly in any condition. The whole transponder chip is implemented in a 0.18 mu m CMOS process, with a die size of 900 x 800 mu m(2). Our measurement results show that the total power consumption of the tag chip is only 6.8 mu W, with a sensitivity of -13.5 dBm.