Rf/Analog Performance Of Novel Junctionless Vertical Mosfets

In this paper, we analyze the radio frequency (RF) performance for novel junctionless verticalMOSFETs (JLVMOS) with different thicknesses of silicon pillar (T-Si = 5, 10 nm). In addition, a junctionless planar SOI MOSFET is also designed for the comparison in this work. According to the numerical simulations, the JLVMOS of T-Si = 5 nm gets the highest in g(m) and g(m)/I-DS, but the T-Si = 10 nm one gets the highest in A(VI). Moreover, due to the double-gate (DG) structure of the VMOS, it can increase the gate controllability over the channel region.