Methodology For Overlay Mark Selection

It is known that different overlay mark designs will have different responses to process setup conditions. An overlay mark optimized for the 45nm technology node might not be suitable for wafers using 30nm or 20nm process technologies due to changes in lithography and process conditions. As overlay control specifications become tighter and tighter, the process engineer requires metrics beyond precision, tool-induced shift (TIS) and TIS variability to determine the optimal target design. In this paper, the authors demonstrate a novel, comprehensive methodology which employs source of variance (SOV) to help engineers select the best overlay marks to meet overlay control requirements.