Integrated VDMOS transistor with reduced JFET effect

Hedi Hakim, D Bolognesi,Freddy De Pestel

Proceedings of the European Solid-State Device Research Conference（2006）

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摘要

in order to improve the trade-off between the breakdown voltage and the ON-state resistance of integrated VDMOS transistors, an anti Junction Field Effect implant has been introduced for an 80V Smart Power platform based on a 0.35 mu m CMOS node. Optimized dose and energy allow a reduction of the resistance without significant impact on the breakdown voltage and the other integrated components of the technology.

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关键词

breakdown voltage,cmos integrated circuits

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