Scalability Of Split-Gate Charge Trap Memories Down To 20nm For Low-Power Embedded Memories

In this work, split-gate charge trap memories with electrical gate length down to 20nm are presented for the 1st time. Silicon nanocristals (Si-ncs), or silicon nitride (Si3N4) and hybrid Si-nc/SiN based split-gate memories, with SiO2 or Al2O3 control dielectrics, are compared in terms of program erase and retention. Then, the scalability of split-gate charge trap memories is studied, investigating the impact of gate length reduction on the memory window, retention and consumption. The results are analyzed by means of TCAD simulations.