Extending Dual Stress Liner Process To High Performance 32nm Node Soi Cmos Manufacturing

Minghui Cai,Brian J Greene,J Strane,Michael P Belyansky,F Tamweber,D Lee,H Van Meer,E Laffosse,S Luning,D Mocuta, E Maciejewski

2008 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS（2008）

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摘要

Dual stress liner process for high performance SOI CMOS technology at 32nm technology node is improved through the use of dep-etch-dep, etch back, and spacer removal techniques. The stress benefit of DSL is preserved with improved gap fill for the manufacturing of sub-32nm gate length transistors.

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关键词

cmos integrated circuits,dep,silicon on insulator,logic gates,tensile stress,stress,cmos technology,dsl

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