Salvo Process For Sub-50 Nm Low-V-T Replacement Gate Cmos With Krf Lithography
INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST(2000)
摘要
We present the SALVO CMOS process, first device data and simulation study with the following features: (1) self-aligned local channel implants for SCE reduction; (2) sub-50 nm fabrication using only current production tools; (3) replacement gate with dual-polysilicon for low V-T; (4) low aspect-ratio gates with CD insensitive to lithography and etch profile variability. The first demonstration of SALVO process shows it is a viable candidate for future ULSI CMOS production, in view of its versatility, controllability and compatibility.
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关键词
cmos integrated circuits,aspect ratio,photolithography,ion implantation,etching
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