Power Efficient Odd Parity Generator & Checker Circuits

This paper presents three bit odd parity generator and detector circuits based on low power adiabatic logic technique. The paper proposes a new design approach which is being derived from CMOS. A simulative investigation on the proposed circuit has been carried out in NI Multisim at 0.5 mu m CMOS technology with L=0.5 mu m and W=1.25 mu m. The power consumption is compared with conventional CMOS and two popular standard 2PASCL and Adiabatic array logic technique which shows great improvement in power dissipations.