Power And Noise Aware Test Using Preliminary Estimation
2009 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM(2009)
摘要
Issues oil power consumption and IR-drop in testing become serious problems. Some troubles, such as tester fails clue to too much power consumption or IR-drop, test escapes due to slowed clock cycle, and so oil, can happen in test floors. In this paper, we propose a power and noise aware scan test method. In the method, power-aware DFT and power-aware ATPG are executed based on the preliminary power/noise estimation for test. Experimental results illustrate the effect of reducing IR-drop for both shift and capture mode in scan test.
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关键词
clock cycle,noise reduction,design for testability,estimation,atpg,ir drop,dft,test methods,noise,automatic test pattern generation
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