Clock Recovery and Equalization Techniques for Lossy Channels in Multi Gb/s Serial Links

A fully integrated 8.5 Gb/s multi-standard DFE receiver for SATA, SAS and FC is presented. This work addresses the impact that data storage communication standards have on data equalization and clock recovery. The data storage environment and the implication on receiver architecture are described. Implementation of CMOS high speed circuits is discussed and experiments of realized prototypes are presented. The main design parameters of early-late digital clock recoveries are analyzed, and their relationship to system requirements is investigated. At last, additional architectures for higher communication speeds are introduced, together with their potential application in the data storage environment.