Electrostatic Discharge (Esd) Technology Benchmarking Strategy For Evaluating Esd Robustness Of Cmos Technologies

Steven H Voldman,Warren R Anderson,R A Ashton, M Chaine,Charvaka Duvvury,Timothy J Maloney,Eugene R Worley

1998 IEEE INTERNATIONAL INTEGRATED RELIABIILTY WORKSHOP FINAL REPORT（1998）

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摘要

This paper describes an ESD technology benchmarking strategy for evaluating the ESD robustness of a semiconductor technology. The strategy consists of a set of CMOS "building block" test structures, a matrix of these test structures, electrical characterization parameters, ESD metrics, a standardized failure criteria, and an extraction and testing procedure.

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关键词

CMOS, electrostatic discharge (ESD), wafer level reliability (WLR), test structures, high current characterization

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