Jitter in deep submicron CMOS single-ended ring oscillators

ASIC, 2003. Proceedings. 5th International Conference on（2003）

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摘要

A 1/f ³ phase noise corner frequency of approximately 1 MHz has been observed in phase noise measurements of single-ended ring oscillators in a 0.18μm CMOS process. Consequently, increased loop bandwidth is necessary for PLLs in a deep submicron CMOS process to minimize jitter contributed by the VCO. As a guide to design, the time domain figure-of-merit κ is measured as a function of channel width, length, and inverter stage delay.

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关键词

0.18 microns,PLL,VCO,channel length function,channel width function,deep submicron CMOS,figure-of-merit,inverter stage delay,jitter minimization,loop bandwidth,phase noise measurements,single-ended ring oscillators

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