A Low Power Gps/Galileo/Glonass Receiver In 65nm Cmos

Huijung Kim,Jeong-Hyun Choi,Sang-Yun Lee,Taewan Kim, Jung-Woo Kim,Jong-Dae Bae, Chaehag Yi,Hyunwon Moon

2013 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC)（2013）

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摘要

A low power GPS/Galileo/GLONASS receiver is presented. The single chip supports GPS/Galileo and GLONASS operation simultaneously. To operate both application simultaneously, two mixers and two baseband filters are used. The chip size is 3.24 mm(2) including bonding PAD. The system noise figure ( NF) is 1.95 dB including SAW filter which loss is 1 dB. Power consumption is 23.6 mW for GPS/Galileo operation and 25.4 mW for GLONASS operation from 1.2V supply.

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关键词

component,RF receiver,GPS,Galileo,GLONASS,CMOS,65nm,LNA,Mixer,Channel selection filter

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