A 55 nm Logic-Process-Compatible, Split-Gate Flash Memory Array Fully Demonstrated at Automotive Temperature with High Access Speed and Reliability

Nhan Do, Latt Tee,Santosh Hariharan, Steven Malcolm Lemke,Mandana Tadayoni, William Yang, M T Wu, Jinho Kim, Yuehhsin Chen, Chiensheng Su,Vipin Tiwari, Stephen Zhou, R Qian,Ian Yue

2015 IEEE International Memory Workshop (IMW)（2015）

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摘要

In this paper, a Flash macro designed with high-density arrays of split-gate (SG) SuperFlash® cells, compatibly embedded in a 55 nm Low Power (LP) logic process is demonstrated with full functionality and excellent reliability at automotive temperature range. This split-gate Flash memory technology can be seamlessly and universally embedded in multiple logic process platforms, and can continually be scaled to 40 nm and smaller lithographically nodes, without compromising performance and reliability.

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关键词

logic-process-compatible split-gate flash memory array,automotive temperature,high access speed,reliability,SG SuperFlash cells,high-density arrays,low power logic process,LP logic process,multiple logic process platforms,lithographically nodes,size 55 nm,size 40 nm

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