Layout-Design Methodology of 0.246-¿m 2 -Embedded 6T-SRAM for 45-nm High-Performance System LSIs
S Taniguchi, Tetsuo Fujimaki, Hiroyuki Yamada,Naoki Nagashima, F Matsuoka,T Kuwata,M Saito,Hisashi Inokuma,Shinichi Yamada,Kei Imai,Yukinori Enomoto,Hiroshi Naruse, Toyokazu Kitano,Masayuki Iwai,Manabu Ikeda, Toshiko Hirai, Hiroo Maeda, Katsuya Oshima, Ritsuo Watanabe,Hiroshi Fukui, Y Tsunoda,Mitsuhiro Togo, Saori Kanai,S Shino, Teruhiko Hoshino, K Shimazaki,Masataka Nakazawa,Kazuhiro Nakazawa,Yoko Takasu, Hiro Yamasaki,Kazumasa Sunouchi, Keiko Yoshida, Kazuhisa Ohno,Yu Sogo,Hideaki Nii, T Iwamoto,Shoji Mimotogi, Kei Nagaoka,S Iwasa,S Muramatsu, Shinro Watanabe,R Morimoto,Tetsuya Kimura,Yoshimichi Okayama mag（2007）
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