High Performance Architecture for the Lifting-Based Dwt Used in Jpeg2000

High performance architecture for the lifting-based DWT (discrete wavelet transform) is introduced. It has the flexible configuration and high processing speed. The architecture includes the basic control module (BCM), the address generation unit (AGU), one-dimensional wavelet-processing element (WPE) and memory units (MUs). Because of the employ of the pipelining, the whole system is able to achieve to the higher processing speed. Additionally, power consumption and memory requirements can be reduced due to the use of the embedded data extension. The estimated gates are 6600 and the estimated frequency is 300 MHz in the SMIC 0.18μm technology.