Thermal Modeling and Device Noise Properties of 3D-SOI Technology

This article deals with performance of 3D-IC which is influenced by thermal effects as well as 3D packaging and parasitic effects. Actual circuit performance is difficult to predict as thermal and 3D packaging effects act in opposite ways. To provide design insight, a stacked wafer 3D-SOI technology was characterized and a thermal model was developed. Electro-thermal simulations of 3D-ICs were performed, and simulation results match measured data. Device noise is measured for this technology.