Demonstration of p-type In 0.7 Ga 0.3 As/GaAs 0.35 Sb 0.65 and n-type GaAs 0.4 Sb 0.6 /In 0.65 Ga 0.35 As complimentary Heterojunction Vertical Tunnel FETs for ultra-low power logic

Extremely scaled high-k gate dielectrics with high quality electrical interfaces with arsenide (As) and antimonide (Sb) channels are used to demonstrate complimentary 'all III-V' Heterojunction Vertical Tunnel FET (HVTFET) with record performance at vertical bar V-DS vertical bar=0.5V. The p-type TFET (PTFET) has I-ON=30 mu A/mu m and I-ON/I-OFF=10(5), whereas the n-type TFET (NTFET) has I-ON=275 mu A/mu m and I-ON/I-OFF=3x10(5), respectively. NTFET shows 55mV/decade switching slope (SS) while PTFET shows 115mV/decade SS in pulsed mode measurement. Vertical TFET offers 77% higher effective drive strength than Si-FinFET for given inverter standard cell area. Energy-delay performance of TFET shows gain over CMOS for low V-DD logic applications.