A 28-Gb/s 4.5-pJ/bit transceiver with 1-tap decision feedback equalizer in 28-nm CMOS

A low-power and area optimized 28-nm CMOS 28-Gb/s transceiver is presented. The transceiver comprised with one PLL shared with 4 transceiver lanes. To meet the CEI-28G-VSR and CAUI4 (chip-to-module) standards, a 1-tap DFE is employed for the receiver. The power reduction is realized by employing 1-tap loop unrolled DFE circuits with domino logic and dynamic latches, and eliminating FFE. The transceiver occupies 2.31 mm ² and consumes 505 mW (4.5 pJ/bit).