Advanced ESD tool flow, testing and design verification results

Electrical Overstress Electrostatic Discharge Symposium, 2012.

Cited by: 2|Views18

Abstract:

ESD verification has become increasingly complex as integrated circuits move towards system-on-chip (SOC) applications. The result of this is that newer ESD specific checking techniques are required. This paper describes the ESD checking flow of these tools, the testing of them, and the real design errors they have uncovered.

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