Inspection and metrology for through-silicon vias and 3D integration

3D IC integration employs advanced interconnect technologies including through-silicon vias (TSVs), bonding, wafer thinning, backside processing and fine pitch multi-chip stacking. In 2013, Mobile Wide I/O DRAM is expected to be one of the first high volume 3D IC applications. Many of the manufacturing steps in TSV processing and 3D integration can complicate inspection and metrology. This paper reviews a typical via-mid flow emphasizing the inspection and metrology challenges inherent in 3D integration. A preliminary look at the 2011 ITRS roadmap for 3D interconnect metrology is presented, including the gaps in currently available inspection and metrology tools.