ESD design automation for a 90nm ASIC design system
electrical overstress/electrostatic discharge symposium（2004）
摘要
Design tools for ESD are described that ensure robust protection at both the cell and chip level in a high-volume, highly automated ASIC design system. There are three primary components: Design Rule Checking (DRC) for ESD; transient CDM simulations on extracted netlists; and analysis of chip-level power supply net resistances.
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关键词
metals,chip,electrostatic discharge,application specific integrated circuits,design automation,data mining,design rule checking,integrated circuit design
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