Evaluation of diode-based and NMOS/Lnpn-based ESD protection strategies in a triple gate oxide thickness 0.13 µm CMOS logic technology

In a 0.13 mum CMOS technology, ESD protection solutions based on NFETs and diodes are compared and their applicability for several groups of digital I/Os are discussed. In order to enable the use of these strategies, there are process requirements which need to be considered during the technology definition.