20nm VIA BEOL patterning challenges

Wontae Hwang, Michael D Anderson,Yayi Wei, Matthew Herrick,Xiang Hu, Bumhwan Jeon,Sohan S Mehta, Chienhsien S Lee, Shyam Pal,Mark H Somervell, H H Tsai

ADVANCES IN RESIST MATERIALS AND PROCESSING TECHNOLOGY XXX（2013）

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摘要

Higher density on 20nm logic chips require tighter pitches to be implemented not only at critical metal layers, but at BEOL critical VIA layers as well. Smaller pitches on critical via are no longer achievable through the conventional positive tone development (PTD) process. Instead, negative tone developement (NTD) is considered, evaluated, and integrated as an alternative, along with the double patterning (DP) method. Additionally, preliminary results on NTD+DP patterning challenges, including patterning verification, are presented in this paper.

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关键词

Double patterning (DP),LELE,Critical Via,Negative Tone Development (NTD),BEOL (Back-End-Of-Line) interconnect,Immersion lithography,logic

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