Vlsi Design of Reed-Solomon Decoder Based on New Architecture of Modified Euclidean Algorithm
2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS（2003）
关键词
0.35 microns,500 Mbit/s,65 MHz,CMOS technology,Euclidean algorithm,RS 223,RS 255,RS decoder,Reed-Solomon decoder,VLSI design,data throughput,error-evaluator module,error-locator module,error-probability minimization,mE algorithm
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