Bitline Leakage Compensation (Blc) And Leakage Reduction (Blr) Techniques For 2-3ghz On-Chip Cache Arrays In Microprocessors On 90nm Logic Technology

M Khellah,Yb Ye,D Somasekhar,D Casper,B Bloechel,T Nguyen,G Dermer,K Zhang,G Pandya,A Farhang,V De

2005 Symposium on VLSI Circuits, Digest of Technical Papers（2005）

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摘要

Bitline leakage compensation (BLC) and leakage reduction (BLR) techniques, implemented for cache arrays on a testchip in a 90mn logic technology, demonstrate improvement in operational frequency from 1.2GHz to 2GHz for BLC, and to 3GHz for BLR, with 17% and 10% area impacts, respectively.

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关键词

logic circuits,chip,voltage,calibration,logic design,frequency

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