DSA template optimization for contact layer in 1D standard cell design

At the 7 nm technology node, the contact layers of integrated circuits (IC) are too dense to be printed by single exposure lithography. Block copolymer directed self-assembly (DSA) has shown its advantage in contact/via patterning with high throughput and low cost. To pattern contacts with DSA, guiding templates are usually printed first with conventional lithography, e. g., 193 nm immersion lithography (193i) that has a coarser pitch resolution. Contact holes are then patterned with DSA process. The guiding templates play the role of controlling the DSA patterns inside, which have a finer resolution than the templates. The DSA contact pitch depends on the chemical property of block copolymer and it can be adjusted within a certain range under strong lateral confinement to deviate from the natural pitch. As a result, different patterns can be obtained through different parameters. Although the guiding template shapes can be arbitrary, the overlay accuracy of the contact holes patterned are different and largely depend on the templates. Thus, the guiding templates that have tolerable variations are considered as feasible, and those have large overlays are considered as infeasible. To pattern the contact layer in a layout with DSA technology, we must ensure that all the DSA templates in the layout are feasible. However, the original layout may not be designed in a DSA-friendly way. Moreover, the routing process may introduce contacts that can only be patterned by infeasible templates. In this paper, we propose an optimization algorithm that optimize the contact layer for DSA patterning in 1D standard cell design. In particular, the algorithm modifies the layout via wire permutation technique to redistribute the contacts such that the use of infeasible templates is avoided and the feasible patterns that with better overlay control are favored. The experimental result demonstrate the ability of the proposed algorithm in helping to reduce the design and manufacturing cost of a DSA-enabled process at 7 nm technology node.