Si/Si1−xGex p-Channel Mosfets Fabricated Using a Gate Quality Dielectric Process

The use of Si1−xGex alloys for p-channel high transconductance MOSFETs requires a high quality dielectric system. Direct oxidation of Si1−xGex alloys or even low temperature deposition of SiO2 directly on Si1−xGex results in a very high interface state density. We show that low interface state densities (below 1011 eV−1cm−2) can be obtained using both thermal and PECVD oxides through the use of a thin (6–8 nm) Si cap between the oxide and the Si1-xGex layer. The Si cap layer leads to a sequential turn-on of the Si1−xGex channel and the Si cap channel, as clearly observed in low temperature C-V curves. We show that this dual channel structure can be designed to suppress the parasitic Si cap channel. High quality, fully isolated Si1−xGex p-channel MOSFETs have been fabricated in an integrable, low Dt process using both thermal or PECVD gate oxides and selective UHV/CVD for the Si/ Si1−xGex channels. We show that optimally designed Si/Si1−xGex MOSFETs exhibit up to 70% higher transconductance at 300K than control Si devices fabricated on n-doped 1017/cm3 Si substrates. Si/Si1−xGex p-channel MOSFETs with thermal and PECVD gate oxides show comparable device characteristics.