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Si-Cap-Free Sige P-Channel Finfets and Gate-All-Around Transistors in A Replacement Metal Gate Process: Interface Trap Density Reduction and Performance Improvement by High-Pressure Deuterium Anneal

H. Mertens,R. Ritzenthaler,H. Arimura,J. Franco,F. Sebaai,A. Hikavyy,B. J. Pawlak,V. Machkaoutsan,K. Devriendt,D. Tsvetanova,A. P. Milenin,L. Witters,A. Dangol,E. Vancoille,H. Bender,M. Badaroglu,F. Holsteyns,K. Barla,D. Mocuta,N. Horiguchi,A. V-Y Thean

2015 SYMPOSIUM ON VLSI TECHNOLOGY (VLSI TECHNOLOGY)（2015）

Cited 60|Views52
Key words
silicon-cap-free silicon-germanium p-channel FinFET,gate-all-around transistor,replacement metal gate process,interface trap density reduction,high-pressure deuterium anneal,GAA FET,RMG process,TMAH treatment,HK post-deposition annealing,PDA,NBTI reliability,Si,SiGe,D2
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