Characterization And Model Enablement Of High-Frequency Noise In 90nm Cmos Technology

A new method based on the lumped-element network representation of the pad-set parasitics is developed to extract the intrinsic drain current noise source and gate resistance from raw measurement data instead of direct de-embedding. The length dependence of BSIM noise model is also corrected using a sub-circuit in the model file. With the new method, we can finally integrate an improved and hardware verified noise model into design kits.