A 7T-SRAM with data-write technique by capacitive coupling

A 7-transistor static random access memory (SRAM), in which cell data are written by capacitive coupling, is proposed. In the 7T-SRAM configuration, the traditional read/write port using two pass-gates (PGs), which are used in 6T-SRAM, is eliminated and the read port using two transistors such as 8T-SRAM and the equalizer for the cell node pair are installed. This read port transistor also acts as a coupling capacitor for writing external data after floating paired cell nodes. The elimination of current-drive via PGs in read/write operation solves current-conflict problems. No degradation of static noise margin (SNM) reduces $V_{\mathrm {dd}}$ minimum by 0.1 V in 24-nm 3.3-V high-voltage CMOS process and by 0.3 V in 40-nm standard logic CMOS process. A large coupling transistor design enhances differential cell signal in write, and enables stable operation for scaled SRAMs with large threshold voltage $V_{\mathrm {t}}$ variation. A 7T-SRAM cell size is comparable to that of 6T-SRAM in 24-nm 3.3-V high-voltage CMOS process and 10% smaller than that of 8T-SRAM in 40-nm standard logic CMOS process. A prototype of 64-b 7T-SRAM with 8.74 $\mu \text{m}^{2}$ cell size using 24-nm 3.3-V high-voltage CMOS process has been demonstrated for resistive nonvolatile RAM (NVRAM) page buffer application. The 7T-SRAM macro has achieved 20-ns/10-ns cycle time and 18-ns/10-ns access time at 1.5 V/1.8 V $V_{\mathrm {dd}}$ , and also has realized 100% macro yield in a wafer and low soft error rate (SER) of 400 FIT/Mb at 1.6-V $V_{\mathrm {dd}}$ minimum, which is equal to $\vert V_{\mathrm {tp}}\vert +\vert V_{\mathrm {tn}}\vert $ for 0.1- $\mu \text{A}$ low standby current.