Study Of Factors Limiting Esd Diode Performance In 90nm Cmos Technologies And Beyond

The on-resistance and failure current of Electrostatic Discharge (ESD) protection diodes in 90nm and 65nm bulk CMOS technologies is determined largely by the resistance and failure of metal lines, contacts or vias. With design optimization, P+/NWell ESD diodes fabricated in a 90nm bulk CMOS technology achieved a forward voltage drop of 1.66V at 2A, an on-resistance of 0.27ohms and a 100ns TLP failure current greater than 5A with a junction capacitance of only 125fF, area of 330 mu m(2) and anode perimeter of 300 mu m.