Performance investigation of short-channel junctionless multigate transistors

international conference on ultimate integration on silicon(2011)

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摘要
We investigate the performance of short channel junctionless gate-all-around (GAA) transistors, by comparing the I_V characteristics, subthreshold swing and drain-induced barrier lowring (DIBL) of junctionless GAA transistors with accumulation-mode GAA transistors. We also compare the I_V characteristics of junctionless GAA transistors for different wafer and transport orientations. MuGFETs are investigated for different wafer and channel orientation.
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关键词
transistors,semiconductor device modeling,process model,solid modeling,doping,drain induced barrier lowering,logic gate,field effect transistors,logic gates
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