Optimization of AICu Wiring Delay in Advanced CMOS Technology

Stamper A. K.,McGahay V., Shapiro M.,Miller L. A.,Tian X.,Bryant A., Serianni L. A.

MATERIALS RESEARCH SOCIETY SYMPOSIUM PROCEEDINGS（2011）

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摘要

Fluorinated high-density plasma and plasma-enhanced CVD SiO2 inter-metal dielectrics have been evaluated for 0.50- through 0.25- μm generation CMOS. Several integration issues are discussed, including the impact of fluorine-doped SiO2 on the yield, reliability, and RC delay of 0.7 - 1.8 μm pitch back-end-of-the-line AlCu/tungsten-stud wiring.

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