Use Of Programmable Logic In A Pipelined Trigger For Atlas

We present an overview of the Jet and Energy Sum processor for the ATLAS Level-1 Trigger. The design system is based on the use of commercial off-the-shelf components, including large programmable logic devices. The architecture of the system is discussed, including implementation details that reduce latency and board complexity, and take advantage of the inherent flexibility in the design. The results of technology demonstrator programs confirm the feasibility of key elements of the processor design.