Threshold-Voltage Anomaly In Sub-0.2 Mu M Dram Buried-Channel Pfet Devices

Measurements and simulation have been used to study threshold-voltage (V-t) dependence on gate oxide thickness (tb,) for long-channel buried-channel (BC-) pFET devices in sub-0.2 mum CMOS technologies. The combination of the dual gate oxide process using N-2 implantation to create the thinner gate oxide and well RTA results in the thinner t(ox) devices having higher V-t, contrary to expectation (V-t-t(ox) anomaly). Detailed analysis of doping profiles, depletion contours, and electric potential confirms this anomaly both in the enhancement and depletion modes of operation. These studies show that a balance of net doping between that near the surface and that around the BC-layer is a stringent requirement for the Vt control in BC-pFETS.