A 0.094um² high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist

A 0.094μm ² 8T SRAM bitcell is developed for a 14nm technology featuring FinFET transistors with a 70nm contacted gate pitch [1]. The bitcell and supporting circuitry are optimized for high density and aging tolerance. Supply collapse and wordline boosting techniques are applied for write V _MIN assist. A delayed keeper is used for read V _MIN improvement. A 400MHz V _MIN of 560mV is achieved with the proposed design at -10°C in volume manufacturing.