Implementation Of A Pldro With A Fractional Multiple Frequency Of Reference

A PLDRO (Phase Locked Dielectric Resonator Oscillator) with the output frequency of a fractional multiple of reference is proposed and implemented. The key element in the proposed PLDRO is an image rejection mixer placed between a VCDRO (Voltage Controlled Dielectric Resonator Oscillator) and SPD (Sampling Phase Detector). The image rejection mixer shifts the coupled signal from the VCDRO before the signal feeds the SPD. Therefore, the output frequency of the PLDRO can be realized such that it is not harmonically related with its reference frequency. The frequency divider and multiplier generate the IF frequency for the mixer from the reference frequency. The general PLL (Phase Locked Loop) design parameters such as the damping coefficient and the natural frequency are derived for the proposed topology of the PLDRO. A 7.25 GHz PLDRO with a 100 MHz reference, intended for use as a local oscillator for a ka band Block-up Converter (BUC), is designed and measured. A BJT (Bipolar Junction Transistor) is used as an active component of the VCDRO and a modified two micro-strip line coupled DR model is presented and used for frequency tuning range estimation. The measured phase noise at 10 kHz/100 kHz offset is 101 dBc/Hz and 115 dBc/Hz, respectively. The fabricated PLDRO size is 100 mm by 105 mm by 23 mm including a 100 MHz reference crystal oscillator.