A 20 Gb/s 82mW one-stage 4:1 multiplexer in 0.13 /spl mu/m CMOS

A completely integrated 4:1 multiplexer for high speed operation and low power consumption in 0.13 /spl mu/m CMOS is presented. The circuit uses a new architecture where four data streams are multiplexed in one stage. Pulses with 25% duty cycle select inputs to appear at the MUX-output. The lower number of gates enables low power design. Relaxed timing conditions are additional benefits of the one-stage MUX topology. The MUX works from DC up to 20 Gb/s and consumes 82 mW.