Design considerations of a fast 0-Ω gate-drive circuit for 1.2 kV SiC JFET devices in phase-leg configuration

This paper presents detailed design considerations of an ultra fast gate-drive circuit for 1.2 kV SiC JFET devices in phase-leg configuration using 0-Omega gate resistance. The proposed gate-drive achieved turn-on and turn-off times in the range of 12 to 55 ns operating from a 600 V dc bus with an inductive load of 10 A, and junction temperatures varying from 25 degrees to 200 degrees C. An in-depth experimental evaluation is presented as well fully characterizing the performance attained by the proposed gate-drive circuit.