Byte Slicing Grøstl: Improved Intel AES-NI and Vector-Permute Implementations of the SHA-3 Finalist Grøstl
Communications in Computer and Information Science(2012)
摘要
Grost1 is an AES-based hash function and one of the 5 finalists of the SHA-3 competition. In this work we present high-speed implementations of Grost1 for small 8-bit CPUs, and large 64-bit CPUs with the recently introduced Intel AES-NI and AVX instruction sets. Since Grost1 does not use the same MDS mixing layer as the AES, a direct application of the AES instructions seems difficult. In contrast to previous findings, our Grost1 implementations using the AES instructions are currently by far the fastest known. To achieve optimal performance we parallelize each round of Grost1 by taking advantage of the whole bit width of the used processor. This results in the parallel computation of 16 Grost1 columns using 128-bit registers, and 32 Grost1 columns using 256-bit registers. This way, we get implementations running at 12.2 cylces/byte for Grost1-256 and 18.6 cylces/byte for Grost1-512.
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关键词
Hash function,SHA-3 competition,Grost1,Software implementation,Byte slicing,Intel ABS new instructions,8-bit AVR
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