Simulation and Experimental Evaluation of a Soft Error Tolerant Layout for SRAM 6T Bitcell in 65nm Technology

In this paper, a new layout for SRAM 6T bitcell is presented. The new layout is a simple modification over the traditional 6T layout, but it has demonstrated better soft error tolerance over the traditional layout in radiation experiments. The area of the new layout is 31 % larger than the traditional layout. In TCAD simulation, it demonstrates over 2× smaller error cross section than the traditional layout. In alpha particle and proton experiments, its soft error rate can be reduced up to 73 % compared to the traditional layout.