Wafer Level High Temperature Reliability Study By Backside Probing F Or A 50um Thin Tsv Wafer

Wafer level reliability of TSV has been studied with respect to FEOL (Front end of line) and BEOL (Back end of line) reliability aspects. TSV keep out zone (KoZ) study has been done with varying gate length and width of transistor. Voltage ramp stress (VRS) analysis has been done by varying gate voltage for different KOZ for both SG and EG oxide devices and found not significant impact to device performance. Testing is done for both thick and thin (50um) wafer and found little effect due to wafer thinning. Wafer level FEOL reliability tests are done at 125 deg C and for a 50um thin wafer, a new methodology by probing the device from back side through TSV with a carrier wafer is demonstrated. Probing of the device from the backside of the device eliminate the thin wafer de-bonding from the carrier wafer and mounting onto a dicing tape. With new methodology reliability of the wafer is improved by eliminating thin waferde-bonding and also able to test the thin wafer at higher temperature 125degC which was not possible with wafer on a dicing tape which can withstand only temperature up to 60degC.